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LHF08CTE
V CC =5V±0.5V, 5V±0.25V, T A =-40°C to +85°C
33
V CC =5V±0.25V
LH28F008SCH-
L85 (6)
Versions (5)
V CC =5V±0.5V
LH28F008SCH-
L90 (7)
Sym.
Parameter
Notes
Min.
Max.
Min.
Max.
Unit
t AVAV
Write Cycle Time
85
90
ns
t PHWL
t ELWL
t WLWH
t PHHWH
t VPWH
t AVWH
t DVWH
t WHDX
t WHAX
t WHEH
t WHWL
t WHRL
t WHGL
t QVVL
t QVPH
RP# High Recovery to WE# Going Low
CE# Setup to WE# Going Low
WE# Pulse Width
RP# V HH Setup to WE# Going High
V PP Setup to WE# Going High
Address Setup to WE# Going High
Data Setup to WE# Going High
Data Hold from WE# High
Address Hold from WE# High
CE# Hold from WE# High
WE# Pulse Width High
WE# High to RY/BY# Going Low
Write Recovery before Read
V PP Hold from Valid SRD, RY/BY# High
RP# V HH Hold from Valid SRD, RY/BY#
High
2
2
2
3
3
2,4
2,4
1
0
50
100
100
40
40
5
5
0
25
0
0
0
90
1
0
50
100
100
40
40
5
5
0
25
0
0
0
90
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as
during read-only operations. Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A IN and D IN for block erase, byte write, or lock-bit configuration.
4. V PP should be held at V PPH1/2/3 (and if necessary RP# should be held at V HH ) until determination of block erase,
byte write, or lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed
Configuration) for testing characteristics.
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.
Rev. 1.3
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